﻿ 一种基于FPGA的新型全数字锁相环的建模与分析 Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA

Journal of Electrical Engineering
Vol.03 No.04(2015), Article ID:16487,8 pages
10.12677/JEE.2015.34013

Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA

Bin Yi, Feng Pan, Guoying Lin, Wei Zhao

Electric Power Research Institute of Guangdong Power Grid Corporation, Guangzhou Guangdong

Received: Nov. 16th, 2015; accepted: Dec. 1st, 2015; published: Dec. 8th, 2015

ABSTRACT

This paper proposed a novel all-digital phase-locked loop (ADPLL). By using the self-sampling PI control method, it can obtain a phase-locked output signal without steady-state error and with less jitter. The designed ADPLL is able to adjust the mode number of the digital loop filter according to the phase error between the two input signals of the digital phase detector. In this way, the ADPLL can optimize the lock-in speed when the system stability is also guaranteed. The paper establishes the mathematical model of the ADPLL based on the analysis of the operating characteristic of each module. Using the obtained system transfer function, the paper analyzes the performance parameters of the ADPLL, and provides the guiding principle of the parameters design. The validity of theoretical analysis is verified by experimental test in the final of this paper.

Keywords:All-Digital Phase-Locked Loop, PI Control, Mathematical Modeling, Parameter Analysis

1. 引言

2. 全数字锁相环的构成及其工作原理

Figure 1. Block diagram of the proposed all-digital phase-locked loop

Figure 2. Operation waveform of the proposed all-digital phase-locked loop

3. 全数字锁相环建模及性能参数分析

3.1. 数学建模

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

3.2. 系统性能参数分析

4. 系统实现及性能测试

Figure 3. The block diagram of the linear model for the proposed ADPLL

(a) 时间(ms) (b) 时间(ms)(c) 时间(ms) (d) 时间(ms)

Figure 4. Step response of error transfer function G(z) with different parameters

(a) 动态特性 (b) 稳态特性

Figure 5. Dynamic-state and steady-state performance with a phase jump of −60˚ when kp = 4

(a) 动态特性 (b) 稳态特性

Figure 6. Dynamic-state and steady-state performance with a phase jump of −60˚ when kp = 16

5. 结论

Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA[J]. 电气工程, 2015, 03(04): 99-106. http://dx.doi.org/10.12677/JEE.2015.34013

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